1. Field of the Invention
This invention relates to the formation of a dielectric in integrated circuit devices, and more particularly, to a method of fabricating a super thin O/N/O stacked dielectric by oxidizing a thin nitride layer in low pressure oxygen for high-density DRAMs.
2. Description of the Prior Art
Dynamic random access memory (DRAM) has been widely utilized in integrated circuit (IC) devices and is typically used in computer systems. A conventional memory cell used in high capacity DRAM IC devices includes, as are shown in FIG. 2, a metal-oxide semiconductor field-effect transistor (MOSFET) 10 and a capacitor 12. The gate of the MOSFET 10 is connected to a word line (WL) of the memory IC device. The drain and source regions of the MOSFET 10 are connected, Respectively, to a bit line (BL) of the memory IC device and to ground potential through the capacitor 12. The capacitor 12 of each memory cell is utilized to store data, either a ONE or a ZERO, which is determined by whether or not the capacitor 12 is being charged or discharged. Due to the inherent nature of the DRAM design, the capacitor should have a high capacitance in order to maintain its data for as long a time as possible.
As is well known to persons in this art, the capacitance of the capacitor 12 is directly proportional to the dielectric constant and the surface area of the dielectric layer of the capacitor 12. That is, increasing the surface area or decreasing the thickness of the dielectric layer will increase the capacitance of the capacitor 12. As the density of devices in ICs increases, the area that each device occupies becomes smaller. The resulting smaller capacitors are characterized by a lower capacitance which decreases the time during which the capacitors will store data. Accordingly, it is necessary to use a dielectric with a smaller thickness to improve the capacitance of the capacitors.
In 4 MB and 16 MB DRAM technology, oxide/nitride (O/N) stacked dielectric materials formed by wet-oxidizing a thin nitride (Si.sub.3 N.sub.4) layer for a short duration have been extensively applied to establish a low defect density on the wafer surface and bulk-limited current (which results in a low leakage current and a high breakdown voltage), As currently practiced, such a wet-oxidized nitride cannot be utilized in 64 MB and 256 MB DRAMs because its effective oxide thickness cannot be reduced below 55 .ANG.. Hence, a tantalum pentoxide (Ta.sub.2 O.sub.5) dielectric having a high dielectric constant was studied by G. Q. Lo et al, IEEE Electron Device Letter, vol. EDL-14, no. 5, pp. 216-218 to meet the requirement of 64 MB and 265 MB DRAMs. However, the high leakage current exhibited by a tantalum pentoxide dielectric is still a problem to be solved.